Passivation stack on a crystalline silicon solar cell

ABSTRACT

A method for manufacturing a passivation stack on a crystalline silicon solar cell device. The method includes providing a substrate comprising a crystalline silicone layer such as a crystalline silicon wafer or chip, cleaning a surface of the crystalline silicon layer by removing an oxide layer at least from a portion of one side of the crystalline silicon layer, depositing, on at least a part of the cleaned surface, a layer of silicon oxynitride, and depositing a capping layer comprising a hydrogenated dielectric material on top of the layer of silicon oxynitride, wherein the layer of silicon oxynitride is deposited at a temperature from 100° C. to 200° C., and the step of depositing the layer of silicon oxynitride includes using N 2 O and SiH 4  as precursor gasses in an N 2  ambient atmosphere and depositing silicon oxynitride with a gas flow ratio of N 2 O to SiH 4  below 2.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation-in-part of U.S. patent applicationSer. No. 15/037,163 having a filing date of May 17, 2016, entitledPASSIVATION STACK ON A CRYSTALLINE SILICON SOLAR CELL, which claimspriority under 35 U.S.C. §371 to International Application NumberPCT/NO2014/050215, filed Nov. 19, 2014, which application is related toand claims priority from Norwegian Patent Number 20131549, filed Nov.19, 2013, the entirety of all of which are incorporated herein byreference.

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

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FIELD OF INVENTION

The present invention relates to a method for manufacturing apassivation stack on a crystalline silicon solar cell device. Morespecifically the invention relates to passivating a crystalline siliconsolar cell by means of a thermally stable passivation stack manufacturedby means of a method according to the invention. The invention alsorelates to a crystalline silicon solar cell device obtainable by meansof a method according to the invention.

BACKGROUND OF THE INVENTION

In the following, silicon shall mean crystalline, potentially doped,silicon if not stated otherwise. A person skilled in the art willunderstand that a crystalline silicon chip or wafer, when used as abasis for a solar cell, will be purposively doped to make the siliconp-type or n-type. Further, a person skilled in the art will alsounderstand that dielectric layers mentioned in the following, might,depending on the means of deposition, include elements not shown in thestoichiometric formula. For instance, if deposited by means of chemicalvapour deposition, the various dielectric layers might include hydrogenoriginating from one or more of the precursor gasses. The person skilledin the art will also understand that said dielectric layers may beamorphous or crystalline, depending of the deposition conditions andmeans.

The following references to other publications are indicated withreference numerals in square brackets, whereby relevant text of suchreferences are included as parts of this disclosure as they containtechnical information that person skilled in the art may find useful forunderstanding the background of the present invention.

The key parameter ratio for producing cost-effective solar cells is thecost per watt of output effect, e.g. dollar per watt. There are two waysof reducing the cost per watt; by increasing the efficiency of a solarcell and by reducing the cost of production.

Good surface passivation with a low surface recombination velocity is aprerequisite for obtaining high efficiency in silicon solar cell devicesin which high minority carrier lifetime is of essence. Severaldielectric materials are known which can be used, either alone or incombination, to passivate the surface of a silicon wafer or chip forobtaining reduced surface recombination. Examples of such layers aresilicon nitride (SiN_(x)), amorphous silicon (a-Si), aluminium oxide(Al₂O_(x)) and thermally grown silicon oxide (SiO₂). Further, stackedcombinations of two or more of the mentioned dielectric layers, such asSiN_(x)/a-Si; SiN_(x)/SiO₂ and SiN_(x)Al₂O_(x), have also been shown toprovide good surface passivation quality.

During the manufacturing of crystalline silicon-based solar cells, thesolar cells are usually exposed to one or more process steps at hightemperatures, typically in the range of 800° C. and above. One suchprocess step is the firing, i.e. activation, of printed contacts to makea good connection between the contacts and a p-n junction provided inthe wafer. In the presence of any dielectric passivation and/oranti-reflection layers, the contacts will typically have to be firedthrough the mentioned layers, entailing that the dielectric layers haveto withstand the high temperature without losing the qualities enablingits intended purpose.

A-Si, alone or in a stack with SiN_(x) or SiO₂, has been shown to give aclose to perfect passivation of a crystalline silicon surface. However,studies have shown that a-Si loses its passivation properties if heatedto above 500° C. [1]. A-Si also has a very high optical absorption inthe lower wavelength range of visible light, and any a-Si layer on thefront of a solar cell may therefor “steal” an amount of the incominglight. Thermal oxidation of silicon might also provide good surfacepassivation. However, the growth of such a SiO₂ layer requires hightemperature over a prolonged period of time, which is unwanted forlow-cost production due the amount of energy required for heating. Inaddition, the thermal budget also increases diffusion of impurities inthe silicon, which usually is of sub-electronic grade when used forsolar cells. The impurity migration might significantly degrade theminority carrier lifetime in the silicon, and thus the efficiency of asilicon solar cell. SiN_(x) has been shown to give a decent passivationof crystalline silicon, but when used on p-type silicon wafers therehave been problems with parasitic shunting due to the high positivecharge in the SiN_(x) layer [2]. More recently, Al₂O_(x) with negativecharge has been shown to provide very good surface passivation forp-type crystalline silicon [3]. However, Al₂O_(x) is usually depositedby means of atomic layer deposition (ALD), which requires very highvacuum, and which has been challenging to incorporate with the rate ofmass production usually envisaged for solar cell manufacturing.

Silicon oxynitride (SiO_(x)N_(y)) has been shown to be a promisingdielectric material for surface passivation of silicon [4, 5]. It hasalso been investigated to use SiO_(x)N_(y) in a stack with SiN_(x) forsurface passivation in photovoltaic applications [6]. However, thepassivation quality reported so far has not been sufficient to obtainsatisfactory low surface recombination velocities. Further, the thermalstability of SiO_(x)N_(y) has been a challenge, and the passivationquality has generally degraded after high temperature treatment, such ascontact firing. Deposition temperatures of SiO_(x)N_(y) have generallybeen in range of 250° C. and above.

SUMMARY OF THE INVENTION

The invention has for its object to remedy or to reduce at least one ofthe drawbacks of the prior art, or at least provide a useful alternativeto the prior art.

The object is achieved through features which are specified in thedescription below and in the claims that follow.

The manufacturing of solar cells as such is considered as known to theperson skilled in the art, and the invention will only be discussed inas far as it differs from the prior art.

In a first aspect the invention relates to a method for manufacturing apassivation stack on a crystalline silicon solar cell device, the methodcomprising the steps of:

-   -   providing a substrate comprising a crystalline silicone layer,        such as a crystalline silicon wafer or chip;    -   cleaning a surface of the crystalline silicon layer by removing        an oxide layer at least from a portion of one side of the        crystalline silicon layer;    -   depositing, on at least a part of the cleaned surface, a layer        of silicon oxynitride;    -   depositing a capping layer comprising a hydrogenated dielectric        material on top of the layer of silicon oxynitride, wherein the        layer of silicon oxynitride is deposited at a temperature from        100° C. to 200° C., preferably from 100° C. to 150° C., and even        more preferably from 100° C. to 130° C.    -   using N₂O and SiH₄ as precursor gasses in an N₂ ambient        atmosphere; and    -   depositing silicon oxynitride with a gas flow ratio of N₂O to        SiH₄ below 2, preferably below 1, and even more preferably        around 0.5.

The effect of the very low deposition temperature is a significantlyimproved effect passivation and thermal stability, as will be describedin more detail below with reference to the figures.

The combination of precursor gasses used to produce a passivation stackaccording to the first aspect of the invention has been shown to givesurprisingly good passivation results. The applicant's experiments haveshown that high silicon content in the silicon oxynitride is beneficialfor the passivation quality. However, it has also been found that thesensitivity of the passivation quality on the composition of the siliconoxynitride reduces with reduced deposition temperature.

A person skilled in the art will be aware of different ways of removingan oxide from a layer of crystalline silicon. The oxide may be aso-called native oxide of a few nanometres naturally grown on a siliconsubstrate when exposed to an oxygen-containing atmosphere. As examples,the cleaning might be done by means of liquid hydrofluoric acid or bymeans of a plasma etch in a PECVD chamber. In addition, the layer ofcrystalline silicon may be cleaned chemically be means of a full RCAclean, by a piranha etch (mixture comprising sulphuric acid and hydrogenperoxide), or by other known cleaning procedures removing organiccontaminants in addition to the oxide layer.

In one embodiment the step of depositing the layer of silicon oxynitridemay include using plasma-enhanced chemical vapour deposition (PECVD).PECVD has been shown to produce dielectric layers with a highreproducibility, while at the same time being compatible withlarge-scale manufacturing of solar cells. A person skilled in the artwill also understand the layer of silicon oxynitride might be depositedby means of other deposition methods, such as other chemical vapourdeposition techniques and sputtering. The person skilled in the art willunderstand that the silicon oxynitride layer deposited by such means,and at the above-mentioned temperatures will be hydrogenized andamorphous, microcrystalline or mixed-phase.

In one embodiment the step of depositing the layer of silicon oxynitridemay include depositing said layer with a thickness of less than 10 nm,preferably less than 5 nanometres, and even more preferably around 3nanometres. The good passivation quality of silicon oxynitride has beenshown to be realized already with layers with a thickness of only a fewnanometres. Reduced thickness of said layer implies reduced depositiontime. Further, a layer of silicon oxynitride of less than 10 nanometresfacilitates any subsequent activation/firing of contacts through thelayer of silicon oxynitride. This might be especially beneficial for thesolar cell-related manufacturing processes where, in one of the finalmanufacturing steps, a metal-containing paste is fired through adielectric passivation and anti-reflection coating on top of the solarcell to make contact with a highly doped surface layer of the solarcell. Finally, a thinner layer will also imply less optical absorptionin the layer, i.e. more light entering the solar cell, and thusincreased efficiency.

In one embodiment the step of depositing the capping layer of thehydrogenated dielectric may include depositing said layer with athickness of more than 25 nm, and preferably 40 nm or more. It has beenshown that a dielectric capping layer of a certain thickness isbeneficial for obtaining the maximum passivation quality, and also forimproved thermal stability. The beneficial effect is observed withhydrogenated dielectric layers of a thickness 25 nm and above, with amaximum effect with layers with a thickness of 40 nanometres and above,such as from 40 nanometres to 100 nanometres, including at 75nanometres. The reason is believed to be the need for a sufficientsupply of hydrogen to the layer of silicon oxynitride, from thehydrogenated dielectric layer, for realisation of a chemical passivationeffect of the crystalline silicon.

In one embodiment the step of depositing the capping layer comprisingthe hydrogenated dielectric may include depositing said hydrogenateddielectric layer in the same step as depositing said layer of siliconoxynitride. This may significantly reduce manufacturing time. Asexample, the layer of silicon oxynitride and the capping layer of thehydrogenated dielectric may be deposited by means of the same method andthe same apparatus, such by means of PECVD, and possibly even in thesame PECVD chamber.

In one embodiment the step of depositing a capping layer comprising ahydrogenated dielectric includes depositing a layer of hydrogenatedsilicon nitride. Experiments have shown that hydrogenated siliconnitride may be especially well suited as a capping layer for siliconoxynitride for the purpose of achieving good surface passivation forsolar cells. Silicon nitride is also frequently used, either alone or ina stack, as an anti-reflection coating on solar cells. Hence, thecombination of silicon oxynitride with a capping layer comprisingsilicon nitride may be very well suited both for passivation and foranti-reflection purposes. The thickness of the silicon nitride may betailored so as to optimize the anti-reflection properties of a solarcell as will be known to a person skilled in the art. Silicon nitridemay be used as the sole deposited capping layer, or it may be used in astack with other dielectrics, such as with non-thermal silicon oxide.

In one embodiment the method, after the deposition of the layer ofsilicon oxynitride and the hydrogenated dielectric capping layer, maycomprise the step of heating the crystalline silicon substrate at atemperature of above 700° C., preferably around 800° C. Peak heating maylast for a few seconds, typically 2-4 seconds.

In one embodiment the method also relates to the manufacturing of asilicon solar cell, the method comprising any embodiment of the methodfor the manufacturing of the silicon solar cell device discussed above.

A layer of silicon oxynitride deposited by means of any embodiment ofthe invention as mentioned above has been shown to be particularlystable under subsequent high temperature steps. In contrast to siliconoxynitride layers deposited by means of methods according to prior art,a silicon oxynitride layer deposited by means of a method according tothe present invention maintains or even improves its passivationqualities after being exposed to high temperature manufacturing steps,which typically corresponds to temperatures used for contact firing asmentioned above.

In a second aspect the invention relates to a crystalline silicon solarcell device obtainable by means of a method according the abovedescription.

In a third aspect the invention also relates to a crystalline siliconsolar cell comprising the above-mentioned solar cell device. Theapplicant has performed tests showing a significant efficiency gain fora solar cell comprising a passivation stack deposited by means of amethod according to the first aspect of the invention compared to asolar cell without the layer of silicon oxynitride. In particular, theapplicant has performed experiments showing a 0.4% absolute efficiencygain for a multi-crystalline Si solar cell comprising aSiN_(x)/SiO_(x)N_(y) stack compared to a similar solar cell with aSiN_(x) layer only.

Another significant advantage of a solar cell according to the thirdaspect of the invention has been shown to be an improved resistance topotential induced degradation (PID) when using such a solar cell in asolar module. PID is an undesirable effect sometimes occurring in solarcells and modules and often leading to unexplainable yield losses. Theyield losses are typically seen as reduced shunt resistances and thus aloss in a module's maximum power point and open-circuit voltage. Onesource of PID has been found to be mobile sodium ions diffusing from thefront glass of a module to the cell surface due to a force caused bypotential induced stress, though the mechanisms involved once the sodiumions reach the silicon are not well understood [7]. The presentapplicant has found, through experimental studies, that silicon solarcells according to the third aspect of the invention, i.e. havingpassivation stacks as prepared by means of a method according to thefirst aspect of the invention, have a significantly improved resistanceto PID compared to silicon solar cells without said passivation stack.The experiments were performed by means of a PIDcon from FreiburgInstruments GmbH. The silicon solar cells used were p-type multicrystalline cells with an anti-reflection coating of hydrogenizedsilicon nitride. The cells were prepared with and without a layer ofsilicon oxynitride between the anti-reflection coating and thesubstrate, the former type thus representing a silicon solar cellaccording to the third aspect of the invention. Modules with siliconsolar cells of either the former or the latter type were tested at atemperature of 60° C. for 24 hours at a voltage of 1000 V. The resultsshowed significantly increased shunt resistances, without degradation,for modules comprising the silicon solar cells according to the thirdaspect of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

In the following are described examples of preferred embodimentsillustrated in the accompanying drawings, wherein:

FIG. 1 shows the effective minority carrier lifetime in variouspassivated crystal-line silicon substrates;

FIG. 2a shows the absorbance as a function of wavenumber in dielectriclayers of different composition before high temperature treatment;

FIG. 2b shows the corresponding absorbance as a function of wavenumberin the same dielectric layers after high temperature treatment;

FIG. 3 shows the extinction coefficient as a function of wavelength fordifferent dielectric layers;

FIG. 4 shows the effective minority carrier lifetime and the depositionrate of silicon oxynitride as a function of deposition temperature;

FIG. 5 shows the effective minority carrier lifetime as a function ofthe thickness of the silicon oxynitride layer; and

FIGS. 6a-6d show different embodiments f silicon solar cells accordingto the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Silicon wafers used in the experiments were cleaned by a piranha etchand a subsequent removal of oxide in hydrofluoric acid. Both siliconoxynitride SiO_(X)N_(Y) and a capping layer of hydrogenated siliconnitride (SiN_(x) for simplicity) were deposited by means of PEVCD, inthe same PECVD chamber. In the experiments the SiO_(x)N_(y) layer wasdeposited with SiH₄ and N₂O as the precursors in N₂ ambient.Alternatively, the SiO_(x)N_(y) layer may be deposited with SiH₄ and N₂Oas the precursors in an Ar ambient atmosphere, or with no ambientatmosphere. The flow ratio of N₂O to SiH₄ was varied from 0:13 to1000:13, resulting in different stoichiometric SiO_(x)N_(y) layers,ranging from hydrogenated amorphous silicon (a-Si) through SiO_(x)N_(y)to silicon oxide (SiO_(x)). SiO_(x)N_(y) was deposited at temperaturesranging from 100° C. to 400° C. with a thickness from 1 to 40 nm andabove. The temperature was measured in the deposition chamber as will beunderstood by a person skilled in the art. The capping layer ofhydrogenated SiN_(x) was deposited with SiH₄ and NH₃ as the precursorgasses.

The deposition temperature was varied from 130° C. to 400° C. and theflow ratio of SiH₄ to NH₃ was varied from 20:20 to 45:20, resultingSiN_(x) layers with different reflective index. After depositing theSiN_(x)/SiO_(x)N_(y) stack, some of the passivated samples wereheated/annealed in a belt furnace with a peak temperature of 800° C. for3 s, corresponding to a standard contact firing step during themanufacturing of crystalline silicon solar cells.

FIG. 1 shows the effective minority carrier lifetime, T_(eff) inmicroseconds, for both p- and n-type crystalline silicon waferspassivated using a stack of SiN_(x)/SiO_(x)N_(y) according to thepresent invention and compared with a standard passivation of a singlelayer of hydrogenated SiN_(x), both before firing, shown in opencolumns, and after firing, shown in hatched columns. In this experimentthe SiO_(x)N_(y) layer was deposited with a N₂O:SiH₄ ratio of 20:45. TheSiN_(x) layer had a thickness of 75 nm. The p-type wafers were ofFloat-Zone (FZ) quality with a resistivity of 1-3 ohm·cm, while then-type wafers were of Czochralski (CZ) quality with a resistivity of 1-3ohm·cm. T_(eff) was measured by means of Quasi steady-state photoconductance at an injection level of 10¹⁵ cm⁻³, as is also the case forthe other effective minority carrier lifetime data disclosed herein. Ascan be seen from the figure, both the p- and n-type silicon material,with the SiN_(x)/SiO_(x)N_(y) passivation, demonstrate minority carrierlifetimes in the millisecond range, both for as-deposited and after hightemperature annealing, with an increased lifetime after annealing. Thelifetime is significantly improved compared to the reference sample withonly SiN_(x) passivation. The minority carrier lifetime after annealing,for the samples passivated by SiN_(x)/SiO_(x)N_(y), was 2.3 millisecondand 3.2 milliseconds for the p- and n-type samples, respectively.

In FIGS. 2a and 2b absorbance, A, as a function of wavenumber, ω, isshown as measured by means of Fourier transform infrared spectroscopy(FTIR) of SiO_(x)N_(y) layers of different compositions, before andafter firing, respectively. The results are compared to the absorbancein SiN_(x). The two dominating peaks, C and D, in the Figures arerepresentative of Si—N(a-s) bonds at 835 cm⁻¹ and Si—O(s) bonds at 1080cm⁻¹, respectively, as obtained by the extremes of SiN_(x) at one sideand a flow ratio of 1000:13 of N₂O:SiH₄ on the other side. The twointermediate curves shows the absorbance in layers deposited withN₂O:SiH₄ flow ratios of 20:45 and 20:13. The peak A at 470 cm⁻¹ isindicative of Si—O(r) bonds, the peak B at 640 cm⁻¹ indicates thepresence of Si₃—H(b) bonds, the peak E at 2300 cm⁻¹ indicates Si₃—H(s)bonds, while the peak F at 3400 cm⁻¹ indicates N—H(s) bonds). Even ifthe stoichiometry varies with the different flow ratios the layers seemto be quite stable after the high temperature step, as seen whencomparing FIGS. 2a and 2 b. These results, in combination with theresults from not shown capacitance-voltage measurements, indicate thatthe passivation is obtained mostly from chemical passivation of danglingbonds at the crystalline silicon surface.

The optical properties of the SiO_(x)N_(y) also vary with depositionconditions, as indicated in FIG. 3, where the extinction coefficient, K,as measured by means of ellipsometry, is shown as a function ofwavelength, λ. In comparison, it is shown that SiO_(x)N_(y) has asignificantly lower absorption than amorphous silicon in the spectralrange up to 600 nanometers. In fact, the absorption of SiO_(x)N_(y) iscomparable to that of low-refractive hydrogenated SiN_(x). Further, thebest passivation results were obtained for SiO_(x)N_(y) layers with arelative high silicon portion, i.e. deposited with a low N₂O:SiH₄ ratio,in this example 20:45.

FIG. 4 shows the minority carrier lifetime, T_(eff) in microseconds, ofthe previously mentioned p-type silicon as well as the deposition rateof SiO_(x)N_(y) as a function of deposition temperature ranging from100° C. to 400° C. T_(eff) is shown both for samples passivated by aSiN_(x)/SiO_(x)N_(y) stack deposited with a N₂O to SiH₄ gas flow ratioof 20:13 and 20:45. The deposition rate shown corresponds to the flowratio of 20:13. As seen from the figure, the minority carrier lifetimeof the sample on which SiO_(x)N_(y) is deposited with the 20:13 gas flowratio obtained a best T_(eff) of 1 millisecond after firing, while thesample with SiO_(x)N_(y) deposited with a flow ratio was 20:45 obtaineda best T_(eff) of 2.3 milliseconds after firing. T_(eff) for bothsamples approximately doubled when lowering the deposition temperaturefrom 400° C. to 130° C. and 100° C., respectively. Another beneficialeffect as seen from the figure, is that the deposition rate alsoincreases with reduced temperature, which is a bit surprising, takinginto account results from the prior art. For instance, keeping the flowratio of N₂O:SiH₄ at 20:13, the deposition rate increases from 0.46 to0.7 nm/s when the deposition temperature was decreased from 400° C. to130° C.

In FIG. 5 the minority carrier lifetime, T_(eff), as a function of thethickness of the SiO_(x)N_(y) layer is shown under in an experimentperformed under sub-optimal conditions. However, the results arebelieved to be valid also for SiO_(x)N_(y) layers deposited at theoptimal conditions mentioned above. There is a peak in minority carrierlifetime at a SiO_(x)N_(y) layer thickness of 3 nm, while the lifetimefor layers thicker than 10 nanometers is comparable to that at 10nanometers.

Also, the deposition conditions of SiN_(x) were shown to influence thepassivation quality of the SiN_(x)/SiO_(x)N_(y) stack. It was found thatthe passivation quality was improved with increasing depositiontemperature of SiN_(x). The best minority carrier lifetime was obtainedwhen the SiN_(x) capping layer was deposited at 400° C., with theminority carrier lifetime shown to increase with the depositiontemperature from 130° C. to 400° C., both before and after firing. Thevariation of flow ratio of SiH₄:NH₃ affects the optical properties ofthe SiN_(x) layer, while the variation was found to have littleinfluence on the minority carrier lifetime. It was found that in orderto optimize the passivation, the SiN_(x) as a capping layer should havea thickness of around 40 nm or above.

FIGS. 6a-6b show various examples of silicon solar cells provided withpassivation stacks according to the present invention are shown. Thefunctionality of such solar cells will be known to a person skilled inthe art and will thus not be discussed in detail herein. The followingfigures are shown simplified and schematic, and the various features inthe Figures are not drawn to scale. Identical reference numeralsindicate identical or similar features in the figures.

In FIG. 6 a, the reference numeral 1 indicates a silicon solar cell of atype that is usually referred to as a standard silicon solar cell. Acrystalline silicon wafer 2 is passivated by means of a first layer 3 ofSiO_(x)N_(y) capped by a second layer 5 of a hydrogenated dielectric,here shown in the form of hydrogenated SiN_(x). In sum the first andsecond layers 3, 5 act as a combined passivation and anti-reflectioncoating on a front surface 21 of the solar cell 1. A thin, highly dopedregion 25 is provided at the front surface 21 so as to constitute a p-njunction/diode together with the base doping of the silicon wafer 2. Aset of front side contacts 7 is provided on top of the first layer 3 onthe front side 21 of the solar cell 1, while a set of back side contacts9 have been provided at a backside 23, contacting a highly dopedbackside region 27. The front side contacts are shown prior to firing,i.e. prior to establishing contact with the highly doped surface region25.

FIG. 6b shows a so-called bifacial solar cell 1 where thepassivation/anti-reflection stack constituted by the first layer 3 ofSiO_(x)N_(y) and the second layer 5 of SiN_(x) is provided on both sidesof the solar cell 1. In alternative embodiments the two layers 3, 5 ofthe passivation stack SiN_(x)/SiO_(x)N_(y) may be provided only on thefront surface side 21 or on the backside 23.

In FIG. 6 c, the two layers 3, 5 of the passivation stackSiN_(x)/SiO_(x)N_(y) are shown as provided on both sides of a passivatedemitter rear contact (PERC) solar cell, while in FIG. 6d the two layers3, 5 are shown used on both sides of a back-contacted back junctionsolar cell. In the latter case, both polarity contacts 7, 9 are providedon the backside 23 of the solar cell, usually in an interdigitatedfinger pattern following the shape of oppositely doped emitter and baseregions 29, 29′. Also in these embodiments the two layers 3, 5 of thepassivation stack SiN_(x)/SiO_(x)N_(y) may be provided only on the frontside 21 or on the backside 23.

What is claimed is:
 1. A method for manufacturing a passivation stack ona crystalline silicon solar cell device, the method comprising the stepsof: providing a substrate comprising a crystalline silicon layer such asa crystalline silicon wafer or chip; cleaning a surface of thecrystalline silicon layer by removing an oxide layer at least from aportion of one side of the crystalline silicon layer; depositing, on atleast a part of the cleaned surface, a layer of silicon oxynitride; anddepositing a capping layer comprising a hydrogenated dielectric materialon top of the layer of silicon oxynitride where the layer of siliconoxynitride is deposited at a temperature from 100° C. to 400° C., thestep of depositing the layer of silicon oxynitride including: using N₂Oand SiH₄ as precursor gasses; and depositing silicon oxynitride with agas flow ratio of N₂O to SiH₄ below
 2. 2. The method of claim 1, whereinthe N₂O and SiH₄ precursor gasses are used in an N₂ ambient atmosphere.3. The method according to claim 1, wherein the N₂O and SiH₄ precursorgasses are used in an Ar ambient atmosphere.
 4. The method according toclaim 1, wherein the step of depositing the layer of silicon oxynitrideincludes using plasma-enhanced chemical vapour deposition.
 5. The methodaccording to claim 1, wherein the step of depositing the layer ofsilicon oxynitride includes depositing said layer with a thickness ofless than 10 nm.
 6. The method according to claim 1, wherein the step ofdepositing the capping layer of the hydrogenated dielectric materialincludes depositing said layer with a thickness of more than 25 nm. 7.The method according to claim 1, wherein the step of depositing thecapping layer comprising the hydrogenated dielectric material includesdepositing said hydrogenated dielectric capping layer in the same stepas depositing the layer of silicon oxynitride.
 8. The method accordingto claim 1, wherein the step of depositing the capping layer comprisingthe hydrogenated dielectric material includes depositing a layer ofhydrogenated silicon nitride.
 9. The method according to claim 1,wherein the step of depositing the capping layer comprising thehydrogenated dielectric material includes depositing the layer at thetemperature of depositing the layer of silicon oxynitride.
 10. Themethod according to claim 1, wherein, after the deposition of the layerof silicon oxynitride and the hydrogenated dielectric material cappinglayer further comprising heating the crystalline silicon substrate at atemperature of above 700° C.
 11. The method of manufacturing acrystalline silicon solar cell according to claim
 1. 12. A crystallinesilicon solar cell device obtainable by the method according to claim 1.13. A crystalline silicon solar cell comprising the solar cell device ofclaim
 12. 14. The method according to claim 1, wherein the step ofdepositing the layer of silicon oxynitride includes depositing siliconoxyitride with a gas flow ratio of N₂O to SiH₄ below
 1. 15. The methodaccording to claim 1, wherein the step of depositing the layer ofsilicon oxynitride includes depositing silicon oxyitride with a gas flowratio of N₂O to SiH₄ of approximately 0.5.
 16. The method according toclaim 1, wherein the step of depositing the silicon layer of oxynitrideincludes depositing said layer with a thickness of less than 5 nm. 17.The method according to claim 1, wherein the step of depositing thesilicon layer of oxynitride includes depositing said layer with athickness of 3 nm.
 18. The method according to claim 1, wherein the stepof depositing the capping layer of the hydrogenated dielectric includesdepositing said layer with a thickness of 40 nm or more.
 19. The methodaccording to claim 1, wherein after the deposition of the layer ofsilicon oxynitride and the hydrogenated dielectric capping layer furthercomprising heating the crystalline silicon substrate at a temperature ofapproximately 800° C.